Cite
HARVARD Citation
Lin, R. (2001). A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits. VLSI design. 12 (3), pp. 377-390. [Online].
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Lin, R. (2001). A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits. VLSI design. 12 (3), pp. 377-390. [Online].