High step‐up DC‐DC converter with reduced voltage stress on devices. (26th December 2018) - Babaei, Ebrahim; Jalilzadeh, Tohid; Sabahi, Mehran; Maalandish, Mohammad; Alishah, Rasoul Shalchi
Summary: The aim of this study is to propose a new nonisolated direct current (DC)–DC converter topology with high voltage gain and low voltage stress across the power devices. The proposed converter comprises a switch and n stages of inductor‐capacitor‐diode ( L‐C‐D ) units. Indeed, the proposed converter is based on the combination of the double‐boost and Single‐ended primary‐inductor converter (SEPIC), which is extended to n stages by adding L‐C‐D units. As a consequence, the proposed converter can generate higher voltage gains with small values of the switch duty cycle, which increase the controllability of the converter. Also, as the number of stages increases, the normalized voltage stress across the power devices is reduced. As a result, the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) switch with low R DS‐on and devices with reduced nominal voltage can be used in the proposed converter. Furthermore, another advantage of the proposed converter is that the percentage of input current ripple is low. The voltage and current stresses of the power devices are analyzed. The circuit performance is compared with other high step‐up structures in the literature in terms of voltage gain and normalized voltage stress. The mathematical analysis and circuit performance of the proposed topology are verified by experimental results.