High‐gain, high‐CMRR class AB operational transconductance amplifier based on the flipped voltage follower. (28th January 2019)

• Record Type: Journal Article
• Authors: Centurelli, Francesco; Monsurrò, Pietro; Trifiletti, Alessandro
• Is Part Of: International journal of circuit theory and applications. Volume 47:Number 4(2019)
• Page Start: 499
• Page End: 512
• Publication Date: 2019-01-28
• Subjects: analog circuits -- class AB -- low power -- low voltage -- operational transconductance amplifier -- sample‐and‐hold; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2599
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of ( g m r 0 ) 4, obtained using a two‐stage structure with cascoded stages, and is a two‐stage Miller‐compensated amplifier employing multipath to remove the positive zero. It has close to rail‐to‐rail output swing (limited by cascoding) and very low common‐mode gain thanks to a replica technique (allowing the use of low‐power common‐mode feedback [CMFB] loops). Ninety‐two decibels of gain and 176 dB of common‐mode rejection ratio (CMRR) without CMFB are achieved using a 40‐nm complementary metal‐oxide semiconductor (CMOS) process. The OTA is used to design a low‐power sample‐and‐hold amplifier (SHA) operating at 5 MSps, a typical application for CMOS OTAs, which has been chosen to verify the proposed circuit's performance and to show that the OTA is robust in Monte Carlo simulations under process variations and mismatches in an actual application. Abstract : A novel class AB OTA is proposed, based on a class AB FVF. The OTA has class AB behavior, high gain, and employs multipath to remove the positive zero; it has close to rail‐to‐rail output swing and very low common‐mode gain thanks to a replica technique; it achieves 92 dB of gain and 176 dB of CMRR in a 40‐nm CMOS process. The circuit is robust under mismatches and suitable for switched‐capacitor circuit applications, as shown by its use in a 5 MSps SHA.