Design of low-voltage shallow-depth differential source coupled logic using feedback and feedforward techniques. (April 2019)

• Record Type: Journal Article
• Authors: Rafiee, M.; Ghaznavi-Ghoushchi, M.B.
• Is Part Of: Microelectronics journal. Volume 86(2019)
• Page Start: 140
• Page End: 149
• Publication Date: 2019-04
• Subjects: Source coupled logic -- Shallow-depth logic -- Differential circuits -- Low-voltage high-performance design; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2019.03.002
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A shallow-depth differential source coupled logic is proposed in this paper, targeting low-voltage high-speed applications. In this logic, the number of transistor stages decreases from supply voltage to ground. This feature offers performance advantage over DCVSL (Differential Cascode Voltage Switch Logic) and DSCL (Differential Static CMOS Logic) styles in a circuit block. Using 180 and 65-nm standard CMOS technologies, the proposed logic demonstrates an average speed-up of 30% over CVSL (Cascode Voltage Switch Logic) based structures in the low-voltage region due to fewer series stages between supply voltage and ground nodes with near EDP (Energy-Delay Product) to its DSCL counterpart. Simulation and post-layout simulation results of 8-bit carry chain generator show that the proposed logic is 31, 23 and 13% faster than the DCVSL, DSCL and MTCML (Multiple-Tailed CML) carry generator chain, respectively. Proposed logic also demonstrates 7% and 6% PDP (power-delay product) reduction than DCVSL and DSCL carry generator chain, respectively.