Effective Lifetime Approaching 1 ms in High‐Resistivity p‐Type Kerfless Multi‐Crystalline Wafers. Issue 4 (18th March 2019)

• Record Type: Journal Article
• Authors: Hofstetter, Jasmin; Fraser, Ray; Jonczyk, Ralf; Ersen, Ali; Sanderson, Laureen; Linton, John; Lorenz, Adam
• Is Part Of: Solar RRL. Volume 3:Issue 4(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2019-03-18
• Subjects: crystalline silicon solar cells -- kerfless wafer growth -- minority carrier lifetime -- resistivity control; Solar energy -- Periodicals; Photovoltaic power generation -- Periodicals; Solar energy -- Research -- Periodicals; Photovoltaic power generation -- Research -- Periodicals; Periodicals; 333.7923
• DOI: 10.1002/solr.201900009
• Languages: English
• ISSNs: 2367-198X

Abstract

Abstract : Kerfless p‐type wafers of varying resistivity are grown with Direct Wafer® technology with precise control of dosing the boron concentration in the melt. Bulk resistivity values at very low boron concentration corresponding to >100 Ω‐cm are achieved. Select wafers are processed into lifetime samples and effective electron lifetimes of up to 847 μs are measured, corresponding to an estimated bulk lifetime above 1 ms. In contrast to ingot‐based wafers, a very tight resistivity distribution can be achieved during continuous growth using Direct Wafer technology at virtually any desired target resistivity, without variations caused by zone refining. Thus, a Direct Wafer product can be customized for a given solar cell architecture by growing each individual wafers at the optimum bulk resistivity and wafer thickness. Efficiency parity with high‐performance cast multi‐crystalline wafers has already been demonstrated on a passivated emitter and rear cell production line at 20.5% efficiency. Abstract : Kerfless p‐type silicon wafers are grown directly from the melt with Direct Wafer technology. Wafer resistivity can be precisely tuned between 1 and 100 Ω‐cm. Effective electron lifetimes up to 847 μs are measured. Synergy with future high‐efficiency cell architectures is discussed, particularly in combination with thin "3D wafers" with a thick border.