Leakage Current and Static Power Analysis of TFET 8T-SRAM Cell. (2019)

• Record Type: Journal Article
• Authors: Gopinath, Anoop; Ytterdal, Trond; Ben Miled, Zina; Meagher, Robert; Rizkalla, Maher
• Is Part Of: Materials today. Volume 7:Part 3(2019)
• Page Start: 878
• Page End: 887
• Publication Date: 2019
• Subjects: SRAM -- TFET -- Leakage Current -- Static Power -- Cadence Virtuoso; Materials science -- Congresses -- Periodicals; 620.1
• DOI: 10.1016/j.matpr.2018.12.088
• Languages: English
• ISSNs: 2214-7853

Abstract

Abstract: Static Random Access Memory (SRAM) is primarily used for design of upper-level memories such as registers and caches due to its speed and reliability. The Gallium-Nitride (GaN) TFET[1] designed by Notre Dame University has a sub-threshold slope closer to 30mV/decade. It operates at 0.6V and has lower static leakage when compared to its' CMOS counterparts. These properties make TFETs a favourable choice for the design of SRAM cells. This paper focuses on the design, verification and analysis of an 8-transistor (8T) SRAM by cell using the Notre Dame University's 20nm GaN TFET device