A design of low leakage cache memory cell for high performance processors. Issue 2 (17th February 2019) - Gupta, Monica; Gupta, Kirti; Pandey, Neeta
Abstract: The noises, when augmented with leakage, destabilize the data stored in cache (SRAM). So, a novel 7T cache memory cell with reduced leakages and improved read and write performance is proposed to address the mentioned issue. The proposed cell with its unique read assist circuit provides SNM-free read operation. It also provides improved write ability by performing a differential write operation. The performance of the proposed cell is compared with the Standard-6T and Dual-VT 7T (DVT-7T) cells at 32nm technology node in the subthreshold region by SPICE simulations. The proposed structure shows significant improvement over other cells in terms of Read Static Noise Margin (RSNM), Write Static Noise Margin (WSNM), Data Retention Voltage (DRV), critical write time (Tcrit ), read current (Iread ) and standby leakage current (Ileak ) values. In addition it uses three MOS transistor based latch structure to reduce area overhead. The Proposed-7T structure improves RSNM, WSNM, Iread and Ileak over Standard-6T cell. Similarly, performance improvement is observed in RSNM, WSNM, Iread, Tcrit ('0'), Tcrit ('1') and Ileak in comparison to the DVT-7T cell. A super cut-off CMOS scheme to reduce leakages further has been employed in the paper. A process corner analysis has been done to capture the effect of process variation on the performance of cells.