A viable approach for limiting fault currents in electric networks. Issue 4 (28th November 2018)

• Record Type: Journal Article
• Authors: Zhang, Xiaoqing; Zhang, Yongzheng
• Is Part Of: IEEJ transactions on electrical and electronic engineering. Volume 14:Issue 4(2019)
• Page Start: 556
• Page End: 560
• Publication Date: 2018-11-28
• Subjects: fault current limiter -- resonance -- PSCAD -- arc discharge -- impedance matching; Electrical engineering -- Periodicals; Electronics -- Periodicals; 621.3
• DOI: 10.1002/tee.22838
• Languages: English
• ISSNs: 1931-4973

Abstract

Abstract : The growth of electric energy demand has resulted in a dramatic increase in the fault currents. To limit the fault currents, a viable approach is proposed in this article. In the approach, a resonance‐type fault current limiter (FCL) is employed. The FCL has a parallel circuit structure composed of a reactor and a capacitor. The key feature of the FCL is based on using a discharge gap to control the inductive reactance of the reactor. During a short‐circuit fault, the breakdown of the discharge gap makes the inductive reactance of the reactor approximately equal to the capacitive one of the capacitor and the resultant parallel resonance produces a high impedance in the fault circuit to limit the fault currents. The experimental model of the FCL is built to measure the limited fault current waveforms. The case study is also carried out by PSCAD (Power Systems Computer Aided Design) simulation, in which the FCL is applied to an actual 500 kV electric network. A desired current‐limiting effect is exhibited in both the experimental measurement and case study. © 2018 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.