Retention characteristics of a nonvolatile latch utilizing a ferroelectric transistor. (February 2019)

• Record Type: Journal Article
• Authors: Mitchell, Cody; Hunt, Mitchell R.; Ho, Fat D.
• Is Part Of: Microelectronics journal. Volume 84(2019)
• Page Start: 122
• Page End: 128
• Publication Date: 2019-02
• Subjects: FeFET -- Ferroelectric -- Ferroelectric devices -- Latches -- Transistor -- Nonvolatile; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2019.01.004
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents retention characteristics and design recommendations for a nonvolatile latch circuit based on a ferroelectric field-effect transistor. In the design, the use of a ferroelectric transistor in a resistive load inverter allows tuning of the circuit for each ferroelectric transistor size. An estimate of the retention time, due to the unique polarization properties of the ferroelectric layer at the gate, is provided for each transistor size. Data collected for three transistor sizes display the possibility of retaining a stored value beyond a 10-year period, with various size transistors indicating 13–38-year retention periods. Switching the ferroelectric layer polarization between two distinct states by applying either negative or positive poling voltages to the gate of the ferroelectric transistor is explored. Experimental results are presented for each transistor, and detailed retention predictions are shown by measured and extrapolated data. Design parameter recommendations are made for optimization of the retention time of the circuit depending on the transistor size.