Low complexity digital background calibration algorithm for the correction of timing mismatch in time-interleaved ADCs. (January 2019)

• Record Type: Journal Article
• Authors: Abbaszadeh, Asgar; Aghdam, Esmaeil Najafi; Rosado-Muñoz, Alfredo
• Is Part Of: Microelectronics journal. Volume 83(2019)
• Page Start: 117
• Page End: 125
• Publication Date: 2019-01
• Subjects: Time interleaved ADC -- Mismatch correction -- Timing error -- Lagrange interpolation -- Hardware implementation; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.11.019
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A low-complexity post-processing algorithm to estimate and compensate for timing skew error in a four-channel time-interleaved analog to digital converter (TIADC) is presented in this paper, together with its hardware implementation. The Lagrange interpolator is used as the reconstruction filter which alleviates online interpolator redesign by using a simplified representation of coefficients. Simulation results show that the proposed algorithm can suppress error tones for input signal frequency from 0 to 0.4 f s . The proposed structure has, at least, 41% reduction in the number of required multipliers. Implementation of the algorithm, for a four-channel 10-bit TIADC, show that, for a 0.4 f s input signal frequency, the Signal to Noise and Distortion Ratio (SNDR) and Spurious-Free Dynamic Range (SFDR) are improved 31.26 dB and 43.7 dB, respectively. Our proposed approximation technique does not degrade the performance of system, resulting in the same SNDR and SFDR as the exact coefficient values. In addition, the proposed structure provides an acceptable performance in the presence of wideband signals.