Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices. (January 2019)

• Record Type: Journal Article
• Authors: Suzuki, Daisuke; Oka, Takahiro; Hanyu, Takahiro
• Is Part Of: Microelectronics journal. Volume 83(2019)
• Page Start: 39
• Page End: 49
• Publication Date: 2019-01
• Subjects: Magnetic tunnel junction device -- Field-programmable gate array -- Lookup-table circuit -- Circuit optimization; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.10.013
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A circuit optimization technique of nonvolatile logic-in-memory (NVLIM)-based lookup table (LUT) circuits in conjunction with magnetic-tunnel junction (MTJ) devices is proposed. Three important points should be considered for the circuit optimization technique of the NVLIM-based LUT circuit. One is optimizing DC and transient characteristics of the read current path, another is minimizing the effect of capacitance of both read-access transistors and write-access transistors, the other is how to design the selector circuit. As a typical example, the NVLIM-based LUT circuits is designed using 55 nm CMOS technology with two types of MTJ devices; the output delay, power and area of the circuit are evaluated. As a result, the output delay in the NVLIM-based 6-input LUT circuit is reduced by 47% compared to that of conventional SRAM-based implementation with 27% lower active power consumption as well as 67% of area reduction.