Designing of ultra‐low‐power high‐speed repeaters for performance optimization of VLSI interconnects at 32 nm. (3rd October 2018)

• Record Type: Journal Article
• Authors: Khursheed, Afreen; Khare, Kavita; Haque, Fozia Zia
• Is Part Of: International journal of numerical modelling. Volume 32:Number 2(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2018-10-03
• Subjects: CNTFET -- interconnect -- power delay product -- repeater insertion -- smart buffer; Electric networks -- Mathematical models -- Periodicals; Electronics -- Mathematical models -- Periodicals; 621.3011
• DOI: 10.1002/jnm.2516
• Languages: English
• ISSNs: 0894-3370

Abstract

Abstract: This paper resolves the performance issue encountered in very‐large‐scale integration interconnects due to downsizing of integrated circuits. Interconnects designed using carbon nanotubes (CNT) are compared with conventional copper interconnect. The propagation delay of very lengthy interconnect wires is ameliorated by interpolating smart buffers as repeaters within the wires. Existing buffer designs are contrived using both CNT and MOS technology for comparison using a different combination of MOS repeater‐Cu interconnect and CNT repeater‐CNT interconnect. Propound buffer uses power gating techniques and automated toggling approach to reduce delay besides mitigating average power consumption. Compared to conventional buffer, PropoundDesign3 brings about dynamic power saving of 99.94% and leakage power saving of 93%, but causes delay penalty. PropoundDesign2 saves dynamic power by 99.86% and leakage power by 88% and offers reduction in delay by 52%. Whereas PropoundDesign1 saves dynamic power by 98% and reduces propagation delay by 64% but on the cost of leakage power consumption. Simulation for 32 nm is done in HSPICE by considering a section of long interconnect line as driver interconnect load system using Stanford SPICE model for CNT and BSIM4 PTM for MOS.