Evaluation of novel carrier substrates for high reliability and integrated GaN devices in a 200 mm complementary metal–oxide semiconductor compatible process. (17th September 2018)

• Record Type: Journal Article
• Authors: Stoffels, S.; Geens, K.; Li, X.; Wellekens, D.; You, S.; Zhao, M.; Borga, M.; Zanoni, E.; Meneghesso, G.; Meneghini, M.; Posthuma, N.E.; Van Hove, M.; Decoutere, S.
• Is Part Of: MRS communications. Volume 8:Number 4(2018)
• Page Start: 1387
• Page End: 1394
• Publication Date: 2018-09-17
• Subjects: Materials -- Periodicals; 620.11
• DOI: 10.1557/mrc.2018.192
• Languages: English
• ISSNs: 2159-6859

Abstract

Abstract: Abstract : In this paper new materials and substrate approaches are discussed which have potential to provide (Al)GaN buffers with a better crystal quality, higher critical electrical field, or thickness and have the potential to offer co-integration of GaN switches at different reference potentials, while maintaining lower wafer bow and maintaining complementary metal–oxide semiconductor (CMOS) compatibility. Engineered silicon substrates, silicon on insulator (SOI) and coefficient of thermal expansion (CTE)-matched substrates have been investigated and benchmarked with respect to each other. SOI and CTE-matched offer benefits for scaling to higher voltage, while a trench isolation process combined with an oxide interlayer substrate allows co-integration of GaN components in a GaN-integrated circuit (IC).