Runtime power-aware energy-saving scheme for parallel applications. (2017)

• Record Type: Journal Article
• Authors: Sundriyal, Vaibhav; Sosonkina, Masha
• Is Part Of: International journal of high performance systems architecture. Volume 7:Number 3(2017)
• Page Start: 129
• Page End: 139
• Publication Date: 2017
• Subjects: dynamic voltage and frequency scaling -- DVFS -- power savings -- throttling -- running average power limit -- RAPL -- power metering; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

Energy consumption has become a major design constraint in modern computing systems. With the advent of petaflops architectures, power-efficient software stacks have become imperative for scalability. Modern processors provide techniques, such as dynamic voltage and frequency scaling (DVFS), to improve energy efficiency on-the-fly. Without careful application, however, DVFS and throttling may cause significant performance loss due to the system overhead. Typically, these techniques are used by constraining a priori the application performance loss, under which the energy savings are sought. This paper discusses potential drawbacks of such usage and proposes an energy-saving scheme that takes into account the instantaneous processor power consumption as presented by the 'running average power limit' (RAPL) technology from Intel. Thus, the need for the user to predefine a performance loss tolerance is avoided. Experiments, performed on NAS parallel benchmarks and large-scale linear system solvers from the pARMS package, show that the proposed scheme saves more energy than the approaches based on the predefined performance loss.