Length separation of single-walled carbon nanotubes and its impact on structural and electrical properties of wafer-level fabricated carbon nanotube–field-effect transistors. (23rd September 2016)

• Record Type: Journal Article
• Authors: Böttger, Simon; Hermann, Sascha; Schulz, Stefan E; Gessner, Thomas
• Is Part Of: Nanotechnology. Volume 27:Number 43(2016)
• Publication Date: 2016-09-23
• Subjects: carbon nanotube -- FET -- length separation -- dielectrophoresis -- chromatography; Nanotechnology -- Periodicals; Nanotechnology -- Periodicals; Nanotechnology; Publications périodiques; Nanotechnologies; Periodicals; 620.5
• DOI: 10.1088/0957-4484/27/43/435203
• Languages: English
• ISSNs: 0957-4484

Abstract

Abstract: For an industrial realization of devices based on single-walled carbon nanotube (SWCNTs) such as field-effect transistors (FETs) it becomes increasingly important to consider technological aspects such as intrinsic device structure, integration process controllability as well as yield. From the perspective of a wafer-level integration technology, the influence of SWCNT length on the performance of short-channel CNT–FETs is demonstrated by means of a statistical and comparative study. Therefore, a methodological development of a length separation process based on size-exclusion chromatography was conducted in order to extract well-separated SWCNT dispersions with narrowed length distribution. It could be shown that short SWCNTs adversely affect integrability and reproducibility, underlined by a 25% decline of the integration yield with respect to long SWCNTs. Furthermore, it turns out that the significant changes in electrical performance are directly linked to a SWCNT chain formation in the transistor channel. In particular, CNT–FETs with long SWCNTs outperform reference and short SWCNTs with respect to hole mobility and subthreshold controllability by up to 300% and up to 140%, respectively. As a whole, this study provides a statistical and comparative analysis towards chain-less CNT–FETs fabricated with a wafer-level technology.