Impact of dynamic voltage scaling and thermal factors on SRAM reliability. Issue 9 (August 2015) - Rosa, F.R.; Brum, R.M.; Wirth, G.; Kastensmidt, F.; Ost, L.; Reis, R.
Abstract: This work investigates the effects of temperature and voltage scaling in neutron-induced bit-flip in SRAM memory cells. Proposed approach allows determining the critical charge according to the dynamic behavior of the temperature as a function of the voltage scaling. Experimental results show that both temperature and voltage scaling can increase in at least two times the susceptibility of SRAM cells to soft error rate (SER). In addition, a model for electrical simulation for soft error and different voltages was described to investigate the effects observed in the practical neutron irradiation experiments. Results can guide designers to predict soft error effects during the lifetime of SRAM-based devices considering different power supply modes. Highlights: We model an SRAM and a power model to study DVS impact on the critical charge. We consider critical charge under dynamic temperature and DVS variations. The critical charge can decrease 5x during a DVS transition. Temperature creates a vulnerability window shortly after the transition.