Low power FinFET content addressable memory design for 5G communication networks. (November 2018)

• Record Type: Journal Article
• Authors: Arulvani, M.; Ismail, M. Mohamed
• Is Part Of: Computers & electrical engineering. Volume 72(2018)
• Page Start: 606
• Page End: 613
• Publication Date: 2018-11
• Subjects: 5G -- Communication -- SRAM -- CAM -- FinFET; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2018.03.002
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Content Addressable Memories (CAMs) are used in diverse applications, such as network protocols used in Wireless Sensor Networks (WSN), text analytics, reconfigurable computing and signal processing applications that require ultra-high speed and very low power consumption. In this work, a novel FinFET CAM using PMOS access transistors, based on PTM–MG transistor models in 22 nm and 14 nm technology is analyzed. Simulation results show that the Independent Gate (IG) FinFET CAM using PMOS access transistor exhibits a 38% improvement in the speed and 48% power consumption reduction compared to the shorted gate (SG) CAM based on 22 nm technology. Similarly, the proposed IG cell achieves a 5% improvement in speed and 50% reduction in power consumption when 14 nm technology is adopted. Hence the proposed IG cell in 14 nm has 6% improvement in speed and 59% less power consumption over 22 nm technology which is suitable for modern 5th generation communication networks.