Concurrent design of active contour for image segmentation using Zynq ZC702. (November 2018)

• Record Type: Journal Article
• Authors: Mewada, Hiren K.; Patel, Amit V.; Mahant, Keyur K.
• Is Part Of: Computers & electrical engineering. Volume 72(2018)
• Page Start: 631
• Page End: 643
• Publication Date: 2018-11
• Subjects: Active contour -- Image segmentation -- Zynq ZC702 FPGA board -- Hardware-software integration; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2018.01.024
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Image segmentation is the fundamental step in various video processing applications like object tracking, pattern recognition, industrial automation, object classification etc. Earlier, low-level curve gradient methods were used for the real time image segmentation where images were processed pixel by pixel. However, the gradient models provide discontinuous edges and are highly sensitive to the noise in the image. High level Mumford–Shah based Active Contour Model (ACM) provides continuous edges and is less sensitive to noise but the complexity in the algorithm and its iterative implementation makes it challenging for the real time applications. This paper investigates the computational complexity and proposes optimum approximation of segmentation with removal of contour initialization. The proposed algorithm is implemented on Xilinx's Zynq ZC702 FPGA board. The removal of contour initialization increased the speed by 10% in software and fixed point implementation on Xilinx provided 80% segmentation accuracy with very low latency of 7.3270 ns per iteration.