Test data compression using Lingering Component Reduction technique for system-on-a-chip applications. (February 2018)

• Record Type: Journal Article
• Authors: Chakrapani, K.; Muthaiah, R.
• Is Part Of: Computers & electrical engineering. Volume 66(2018)
• Page Start: 1
• Page End: 13
• Publication Date: 2018-02
• Subjects: Lingering Component Reduction -- Standard testing -- A reference pattern Don't-care conditions -- Intellectual property cores -- International Symposium on Circuits and Systems'89; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2017.09.002
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: As technology, processes scale up, and design complexities grow, system-on-chip integration continues to rise rapidly. According to these trends, increasing test data volume is one of the largest challenges in the testing industry. In this work, we present a new test data compression method based on a stored set called Lingering Component Reduction (LCR) Code. The test set contains a large number of don't- care that can be exploited to improve the experimental data compression. In this method, a reference pattern is organized, and an adaptability of input pattern with reference pattern is reduced. The Lingering Component estimation based on test pattern contains more don't-care conditions that can be actively reduced to improve the test data compression on the Intellectual Property cores. The simulation results show the performance of experimental data compression ratio and testing time parameters. From the analysis of simulation results, it is proved that the proposed LCR code enhances a compression ratio and reduce the test time follows the International Symposium on Circuits and Systems'89. The comparative results of several benchmark circuits in maximum cases and compared the outputs of the many previous works without a substantial load on the hardware.