Influence of channel configuration on bandwidth of cadmium zinc telluride detector with a cross-strip pattern. (February 2019)

• Record Type: Journal Article
• Authors: Li, Mohan; Abbaszadeh, Shiva
• Is Part Of: Radiation physics and chemistry. Volume 155(2019:Feb.)
• Page Start: 213
• Page End: 216
• Publication Date: 2019-02
• Subjects: Cadmium zinc telluride -- Cross-strip pattern -- Channel configuration -- Application-specific integrated circuit -- Bandwidth; Radiation chemistry -- Periodicals; Radiometry -- Periodicals; Radiation -- Periodicals; Chimie sous rayonnement -- Périodiques; 539.2
• DOI: 10.1016/j.radphyschem.2018.04.015
• Languages: English
• ISSNs: 0969-806X

Abstract

Abstract: The detector readout bandwidth is of paramount importance to achieve a high count rate and thus a high sensitivity. For detectors with the number of readout channels larger than that of the application-specific integrated circuit (ASIC), multiple ASICs are required. In systems with such a readout scheme, it is important to consider the load balance to achieve the highest count rate. In this work, a Monte Carlo simulation was performed to investigate the bandwidths of different load balancing configurations between two ASICs in a cross-strip cadmium zinc telluride detector. It is found that for anode strips, allocating each ASIC to half of the detector area provides a higher bandwidth when compared to allocating ASIC channels to alternate anode channels. Cathodes that are closer to the field of view will trigger more often and require a more complex load balancing scheme. Charge sharing and scattering play a role in the different bandwidths, and the bandwidth of the half-half configuration is 2.82% higher than that of the alternate configuration. Abstract : Highlights: The load balance of ASICs affects the readout bandwidth of CZT detector. Charge sharing and scattering play a role in the achieved bandwidth. For anodes, the bandwidth of the half-half configuration improves 2.82%. Cathodes need calibration to allocate balanced load to different ASICs.