A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered ZrxSi1−xO2 Gate dielectric and improved electrical and hysteresis performance. (10th March 2017)

• Record Type: Journal Article
• Authors: Hung, Chien-Hsiung; Wang, Shui-Jinn; Liu, Pang-Yi; Wu, Chien-Hung; Wu, Nai-Sheng; Yan, Hao-Ping; Lin, Tseng-Hsing
• Is Part Of: Japanese journal of applied physics. Volume 56:Number 4(2017)Supplement
• Publication Date: 2017-03-10
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.7567/JJAP.56.04CG06
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: The use of co-sputtered zirconium silicon oxide (Zr x Si1− x O2 ) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0–150 W and with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si1− x O2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85 Si0.15 O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103 mV/dec) and field effect mobility (33.76 cm 2 V −1 s −1 ).