Hardware design of parallel switch setting algorithm for Benes networks. (2017)

• Record Type: Journal Article
• Authors: Jiang, Yikun; Yang, Mei
• Is Part Of: International journal of high performance systems architecture. Volume 7:Number 1(2017)
• Page Start: 26
• Page End: 40
• Publication Date: 2017
• Subjects: Benes -- parallel algorithm -- hardware -- RTL -- implementation -- synthesis; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

Benes/Clos networks have been used in many areas, such as interconnection network in parallel computers, multiprocessors system, and networks-on-chip. The parallel switch setting algorithm is the key to satisfy the requirements of high performance switching networks. The Lee's routing algorithm is by far the most efficient parallel routing algorithm for Benes networks. However, there is no hardware implementation for this algorithm. In this paper, the Lee's routing algorithm is fully implemented in RTL and synthesised. We have refined the algorithm in data structure and initialisation/updating of relation values to make it suitable for hardware implementation. The simulation and synthesis results of the switching setting circuits for 4 × 4 to 64 × 64 Benes networks confirm that the timing, area, and power consumption of the circuit is consistent with the complexity of the Lee's algorithm. To the best of our knowledge, this is the first complete hardware implementation of the parallel switch setting algorithm which can handle all types of permutations including partial ones.