Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers. (July 2015)

• Record Type: Journal Article
• Authors: Sen, Bibhash; Goswami, Mrinal; Mazumdar, Subhra; Sikdar, Biplab K
• Is Part Of: Computers & electrical engineering. Volume 45(2015)
• Page Start: 42
• Page End: 54
• Publication Date: 2015-07
• Subjects: Quantum-dot Cellular Automata (QCA) -- QCA multiplexer -- Fault tolerant QCA circuit -- Configurable logic block (CLB); Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2015.05.001
• Languages: English
• ISSNs: 0045-7906

Abstract

Graphical abstract: Highlights: A modular design methodology around multiplexer is designed. This work make a trade-off between modular design and its reliability associated with fault tolerance and energy consumptions. Cascading lower order multiplexer to synthesize higher order multiplexer mitigating wire crossing and delay. Application of proposed design in CLB is also done. Abstract: With the rapid advancement in very large scale integration (VLSI) technology, it is the utmost necessity to achieve a reliable design with low power consumption. The Quantum dot Cellular Automata (QCA) can be such an architecture at nano-scale and thus emerges as a viable alternative for the current CMOS VLSI. This work targets design of logic module in QCA. It reports a modular design methodology to build the fault tolerant 2 n :1 multiplexer with optimized wire-crossings, delay and power consumption. A 2:1 QCA multiplexer is proposed as the basic logic module that in turn is utilized to synthesize 4:1 and 8:1 multiplexers. It shows significant achievement in terms of clock speed (36%), wire-crossing (58%), fault tolerance (77.62%) and power consumption over the existing designs. The effectiveness of proposed multiplexer is further established through synthesis of configurable logic block (CLB) for field programmable gate arrays (FPGAs).