A design of low swing and multi threshold voltage based low power 12T SRAM cell. (July 2015)

• Record Type: Journal Article
• Authors: Upadhyay, P.; Kar, R.; Mandal, D.; Ghoshal, S.P.
• Is Part Of: Computers & electrical engineering. Volume 45(2015)
• Page Start: 108
• Page End: 121
• Publication Date: 2015-07
• Subjects: Charge sharing -- Leakage -- Low power -- Static noise margin -- SRAM -- Swing voltage; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2014.10.020
• Languages: English
• ISSNs: 0045-7906

Abstract

Graphical abstract: Proposed low power 12T MTCMOS based SRAM cell. Highlights: A novel low power 12T MTCMOS based SRAM cell is proposed. Charge recycling technique used for reducing the current leakage during transition mode. Use voltage sources to reduce the dynamic power dissipation. Improving the stability of SRAM cell. Abstract: This paper focuses on the design of a novel low power twelve transistor static random access memory (12T SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines, respectively. Reduction in swing voltage reduces the dynamic power dissipation when the SRAM cell is in working mode. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. The charge recycling technique reduces leakage current when the transistors change its state from sleep to active (OFF to ON condition) and active to sleep (ON to OFF condition) modes. Reduction in leakage current causes the reduction in static power dissipation. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. Simulation results of power dissipation, access time, current leakage, stability and power delay product of the proposed SRAM cell have been determined and compared with those of some other existing models of SRAM cell. Simulation has been done in 45 nm CMOS environment. Microwind 3.1 is used for schematic design and layout design purpose.