Architectural design of a Radix-4 CORDIC-based Radix-4 IFFT algorithm and its FPGA implementation. (1st July 2010)

• Record Type: Journal Article
• Authors: Bhattacharyya, Kaushik; Hazra, Anindya; Hatai, Indranil; Banerjee, Swapna
• Is Part Of: International journal of signal and imaging systems engineering. Volume 2:Number 4(2009)
• Page Start: 201
• Page End: 215
• Publication Date: 2010-07-01
• Subjects: CORDIC -- FPGA implementation -- high bit accuracy -- IFFT architecture -- pipelining -- parallelism -- Radix-4 -- real time applications -- field-programmable gate arrays; Signal processing -- Periodicals; Imaging systems -- Periodicals; Information theory -- Periodicals; 621.3822
• Languages: English
• ISSNs: 1748-0698

Abstract

In high speed applications, it is wise to use Radix-4 algorithm, when the number of data points is the power of four, instead of using the conventional Radix-2 algorithm. In this paper a CORDIC based almost multiplier less architecture for a 16 point Radix-4 IFFT is presented. With the concurrent use of pipelining and parallelism, the advantages of minimisation of latency time and the increment of the throughput rate is achieved. The whole Radix-4 CORDIC-based Radix-4 IFFT architecture is implemented on an FPGA device with the accuracy up to 32-bit precision operating frequency at 55 MHz making it suitable for real-time applications.