Macro-models for high-level area and power estimation on FPGAs. (13th February 2006)

• Record Type: Journal Article
• Authors: Jiang, Tianyi; Tang, Xiaoyong; Banerjee, Prith
• Is Part Of: International journal of simulation and process modelling. Volume 2:Number 1/2(2006)
• Page Start: 12
• Page End: 19
• Publication Date: 2006-02-13
• Subjects: macro-models -- high-level synthesis -- area estimation -- power estimation -- FPGAs -- modelling -- RTL operators -- field programmable gate arrays -- register transfer level; Management -- Computer simulation -- Periodicals; Mathematical models -- Periodicals; Operations research -- Periodicals; Simulation methods -- Periodicals; 003.05
• Languages: English
• ISSNs: 1740-2123

Abstract

This paper presents the high-level equation based area and power macro-models for various RTL level operators on FPGAs. The area model is parameterised with the bit width of the device and the power model takes into account input switching activity and input spatial correlation as well as input bit width. These models are derived by actual synthesis of these RTL operators using back-end logic synthesis and place-and-route tools. Compared with the other approaches, our method generated a uniform macro-model for each operator with fewer coefficients and sometimes lower degrees. It is also easier to analyse the power sensitivity to different parameters.