A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes. (28th August 2018)

• Record Type: Journal Article
• Authors: Sharma, Vishal; Vishvakarma, Santosh; Chouhan, Shailesh Singh; Halonen, Kari
• Is Part Of: International journal of circuit theory and applications. Volume 46:Number 12(2018)
• Page Start: 2314
• Page End: 2333
• Publication Date: 2018-08-28
• Subjects: circuit design -- low‐power -- SRAM -- stability -- write ability; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2555
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: In this work, a data‐dependent feedback‐cutting–based bit‐interleaved 12T static random access memory (SRAM) cell is proposed, which enhances the write margin in terms of write trip point (WTP) and write static noise margin (WSNM) by 2.14× and 8.99× whereas read stability in terms of dynamic read noise margin (DRNM) and read static noise margin (RSNM) by 1.06× and 2.6 ×, respectively, for 0.4 V when compared with a conventional 6T SRAM cell. The standby power has also been reduced to 0.93× with an area overhead of 1.49× as that of 6T. Monte Carlo simulation results show that the proposed cell offers a robust write margin when compared with the state‐of‐the‐art memory cells available in the literature. An analytical model of WSNM for 12T operating in subthreshold region is also proposed, which has been verified using the simulation results. Finally, a small SRAM macro along with its independent memory controller has been designed. Abstract : This work proposes a low‐power 12T SRAM cell with the improved write ability against the PVT variations. The proposed cell employs the read decoupling to improve the read stability and data‐dependent feedback cutting to provide the low‐leakage and improved write ability. The incorporated stacking effect further improves the leakage power. Therefore, the proposed 12T cell may be an attractive choice for today's battery‐operated IoT‐enabled system on chip (SoC) applications.