5-Gb/s linear re-driver in 180 nm CMOS technology. (December 2018)

• Record Type: Journal Article
• Authors: Nguyen, Hieu; Comer, Rod; Pham, Phuc; Margala, Martin
• Is Part Of: Microelectronics journal. Volume 82(2018)
• Page Start: 81
• Page End: 91
• Publication Date: 2018-12
• Subjects: Forward scaling -- Programmable CTLE -- Re-driver -- VGA -- 5-Gb/s; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.10.014
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A single lane, dual channel, 5-Gb/s linear re-driver has been developed and fabricated in low cost 0.18-μm CMOS technology. Some techniques have been applied to attain a very power efficient, low complexity re-driver: transistor optimization, forward scaling design, negative Miller capacitance, and inductive peaking. In addition, the re-driver achieves very good linearity thanks to careful ordering of design blocks. To combat with temperature effect and process variation, some techniques such as ratio-based design and the use of proportional to absolute temperature (PTAT) reference current have also been used. The chip only consumes approximately 90 mA in 5-Gb/s bidirectional operation from a single 1.8 V power supply.