An optimised architecture for radix-2 Montgomery modular multiplication on FPGA. (21st February 2012)

• Record Type: Journal Article
• Authors: Issad, Mohamed; Anane, Mohamed; Anane, Nadjia
• Is Part Of: International journal of high performance systems architecture. Volume 3:Number 4(2011)
• Page Start: 175
• Page End: 183
• Publication Date: 2012-02-21
• Subjects: Montgomery modular multiplication -- high performance architecture -- modular arithmetic -- RSA -- FPGA; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

In this paper, the algorithm and the hardware implementation of radix-2 Montgomery modular multiplication (MMM) are presented. The operation's performances depend on the radix and the modulus size. The MMM with big modulus requires a large area for its implementation. The objective of this work is to realise an optimised intellectual property (IP) to perform this operation with a reduced area, independent of the modulus size, dedicated to low rate cryptographic applications. Our architecture uses a fixed data path size w to compute the MMM of two n -bits operands, with n >> w . To store these operands, we use embedded memory blocks (SelectRam), instead of long registers to overcome the routing complexity which is a timing consumer. The arithmetic unit (AU) is optimised at the low level (CLB), resulting in high performances AU. The proposed architecture is suitable to hybrid cryptosystem where both the symmetric and asymmetric cryptographies are used.