FPGA implementation and performance evaluation of an RFC 2544 compliant Ethernet test set. (5th March 2010)

• Record Type: Journal Article
• Authors: Both, Cristiano B.; Battisti, Cristiano; Kuentzer, Felipe A.; Dos Santos, Tatiana G.S.; , Rafael R. Dos Santos
• Is Part Of: International journal of high performance systems architecture. Volume 2:Number 2(2009)
• Page Start: 107
• Page End: 115
• Publication Date: 2010-03-05
• Subjects: performance evaluation -- ethernet test set -- RFC 2544 -- FPGA implementation -- field programmable gate arrays -- performance verification -- ethernet networks; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

With the constant and rapid advances in microelectronics and networking technology, network service providers' needs for tuning up services, in order to attract more subscribers, have become more important. Ethernet technology has improved in terms of communication speed and has established itself as a standard enabling more recently throughput rates in the range of 1-100 Gbps. However, the need for quality services requires Ethernet testers to be not only standard compliant, but also meet performance criteria as specified by the standard. Performance criteria are difficult to prove and typically cannot be accomplished by software due to the limitations of the underlying general purpose hardware as well as the existence of many software layers. In this paper, we propose a design, an implementation and the performance verification achievements of an Ethernet tester compliant with the throughput and latency tests specified by the RFC 2544 for 10/100 Mpbs Ethernet networks. The results showed that the device designed achieved the performance criteria defined by the RFC while it was implemented in a Commercial Off-The-Shelf (COTS) low cost FPGA board. The performance was compared to an existent software implementation and the results showed that the usual limitations added by several hardware and software layers can be overcome by implementing a frame generator, monitor and media access (MAC layer 2) directly in an FPGA device.