Future ILP processors. (15th March 2006)

• Record Type: Journal Article
• Authors: Cristal, Adrian; Llosa, Josep; Valero, Mateo; Ortega, Daniel
• Is Part Of: International journal of high performance computing and networking. Volume 2:Number 1(2004)
• Page Start: 1
• Page End: 10
• Publication Date: 2006-03-15
• Subjects: microarchitecture -- superscalar design -- out-of-order processors -- ILP processors -- reorder buffers -- registers -- instruction queues -- high performance computing -- memory latencies -- instruction level parallelism -- in-flight instructions; High performance computing -- Periodicals; Computer networks -- Periodicals; High performance computing; Periodicals; 004.05
• Languages: English
• ISSNs: 1740-0562

Abstract

Memory speed is growing more slowly than processor speed. This means that processors must spend more and more time waiting for data to arrive from memory. One of the most effective techniques to deal with this effect is to increase the amount of in-flight instructions in the processor, thus allowing for an increased instruction level parallelism when missing instructions occur. With expected latencies of 500 and 1000 cycles, the amount of in-flight instructions needed to sustain performance will have to increase dramatically, and therefore, the microarchitectural elements, such as the reorder buffer, the number of registers and the instruction queues, which depend linearly on this parameter will have to be re-architected to allow such an increased number of in-flight instructions. In this paper, we present several techniques, which try to solve the problems caused by thousands of in-flight instructions.