Dynamic tiling for effective use of shared caches on multithreaded processors. (15th March 2006)

• Record Type: Journal Article
• Authors: Nikolopoulos, Dimitrios S.
• Is Part Of: International journal of high performance computing and networking. Volume 2:Number 1(2004)
• Page Start: 22
• Page End: 35
• Publication Date: 2006-03-15
• Subjects: simultaneous multithreading -- SMT processors -- shared caches -- compilers -- memory hierarchies -- runtime systems -- operating systems -- data cache conflicts -- data cache partitioning -- dynamic tiling -- high performance computing -- multiple threads; High performance computing -- Periodicals; Computer networks -- Periodicals; High performance computing; Periodicals; 004.05
• Languages: English
• ISSNs: 1740-0562

Abstract

Simultaneous multithreaded (SMT) processors use data caches which are dynamically shared between threads. Depending on the processor workload, sharing the data cache may harm performance due to excessive cache conflicts. A way to overcome this problem is to physically partition the cache between threads. Unfortunately, partitioning the cache requires additional hardware and may lead to lower utilisation of the cache in certain workloads. It is therefore important to consider software mechanisms to implicitly partition the cache between threads by controlling the locations in the cache in which each thread can load data. This paper proposes standard program transformations for partitioning the shared data caches of SMT processors, if and only if there are conflicts between threads in the shared cache at runtime. We propose transformations based on dynamic tiling. The key idea is to use two tile sizes in the program, one for single-threaded execution mode and one suitable for multithreaded execution mode and switch between tile sizes at runtime. Our transformations combine dynamic tiling with either copying or storing arrays in block layout. The paper presents an implementation of these transformations along with runtime mechanisms for detecting cache contention between threads and react to it on-the-fly. Our experimental results show that for regular, perfect loop nests, these transformations provide substantial performance improvements.