Optimising long-latency-load-aware fetch policies for SMT processors. (15th March 2006)

• Record Type: Journal Article
• Authors: Cazorla, Francisco J.; Ramirez, Alex; Valero, Mateo; Fernandez, Enrique
• Is Part Of: International journal of high performance computing and networking. Volume 2:Number 1(2004)
• Page Start: 45
• Page End: 54
• Publication Date: 2006-03-15
• Subjects: SMT processors -- simultaneous multithreading -- fetch policy -- long latency loads -- load miss predictors -- multiple threading -- high performance computing -- fetch engine -- memory latencies; High performance computing -- Periodicals; Computer networks -- Periodicals; High performance computing; Periodicals; 004.05
• Languages: English
• ISSNs: 1740-0562

Abstract

Simultaneous multithreading (SMT) processors fetch instructions from several threads, increasing the available instruction level parallelism of each thread exposed to the processor. In an SMT the fetch engine decides which threads enter the processor and have priority in using resources. Hence, the fetch engine determines how shared resources are allocated, playing a key role in the final performance of the machine. When a thread experiences an L2 cache miss, critical resources can be monopolised for a long time, throttling the execution of remaining threads. Several approaches have been proposed to cope with this problem. The first contribution of this paper is the evaluation and comparison of the three best published policies addressing the long latency load problem. The second and main contributions of this paper are that we have proposed improved versions of these three policies. Our results show that the improved versions significantly enhance the original ones in both throughput and fairness.