A partitioned instruction queue to reduce instruction wakeup energy. (23rd January 2006)

• Record Type: Journal Article
• Authors: Ramirez, Marco A.; Cristal, Adrian; Valero, Mateo; Veidenbaum, Alexander V.; , Luis Villa
• Is Part Of: International journal of high performance computing and networking. Volume 1:Number 4(2004)
• Page Start: 153
• Page End: 161
• Publication Date: 2006-01-23
• Subjects: superscalar processors -- out-of-order execution -- instruction window -- instruction wakeup -- low power -- CAM -- partitioned instruction queue -- high performance computing -- energy consumption; High performance computing -- Periodicals; Computer networks -- Periodicals; High performance computing; Periodicals; 004.05
• Languages: English
• ISSNs: 1740-0562

Abstract

Instruction wakeup logic consumes a large amount of energy in out-of-order processors. Existing solutions to the problem require prediction or additional hardware complexity to reduce the energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a new mechanism for instruction wakeup, which uses a partitioned instruction queue (IQ). The energy consumption of an IQ partition (block) is proportional to the number of entries in it. All the blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed instruction for SPEC2000 benchmarks. The energy consumption and timing of the partitioned IQ design are evaluated using CACTI 3 models for a 0.07 µm process. The average energy savings observed were 85% and 92%, respectively, for 64-entry integer and floating-point partitioned IQs.