An evolvable hardware system in Xilinx Virtex II Pro FPGA. (26th April 2007)

• Record Type: Journal Article
• Authors: Vasicek, Zdenek; Sekanina, Lukas
• Is Part Of: International journal of innovative computing and applications. Volume 1:Number 1(2007)
• Page Start: 63
• Page End: 73
• Publication Date: 2007-04-26
• Subjects: field programmable gate arrays -- FPGA -- evolutionary algorithms -- EA -- evolvable hardware -- image operators -- circuit architectures -- image filter evolution -- virtual reconfigurable circuits -- reconfigurable logic -- search algorithms; Evolutionary computation -- Periodicals; Neural networks (Computer science) -- Periodicals; Genetic programming (Computer science) -- Periodicals; Biologically-inspired computing -- Periodicals; Swarm intelligence -- Periodicals; Quantum computers -- Periodicals; 006.3
• Languages: English
• ISSNs: 1751-648X

Abstract

In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro Field Programmable Gate Arrays (FPGAs). Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution by Martinek and Sekanina, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 sec in average.