Exploring speculative procedure and loop level parallelism in SPLASH2. (1st January 2014)

• Record Type: Journal Article
• Authors: Wang, Yaobin; Liu, Zhiqin; Chen, Huarong; Luo, Xia; Bi, Guotang; An, Hong
• Is Part Of: International journal of high performance systems architecture. Volume 5:Number 2(2014)
• Page Start: 84
• Page End: 92
• Publication Date: 2014-01-01
• Subjects: multicore -- thread level speculation -- TLS -- high performance computing -- HPC -- data dependence; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

How to make use of multicore computing resources to accelerate high performance computing (HPC) applications has become a common concern problem. However, HPC applications have not yet been explored in thread level speculation (TLS) thoroughly, especially in the procedure level. This paper proposes a procedure and loop level speculation architecture model for speeding up HPC applications, including its speculative mechanism, analysis method, etc. It also takes several applications from SPLASH2 to analyse their speculative parallel potential together with performance impacting factors. The experimental results show that: 1) the best Barnes application can get a 90.9× speedup in loop level speculation while Lu application can get 40.2× speedup in procedure level speculation; 2) limited parallelism coverage and severe inter-thread data dependence violations badly affect both loop and procedure level speculative parallelism in some HPC applications; 3) It is found that although loop structure is the main source of speculative parallelism, procedure structure can be treated as its important supplement. Especially in applications that their 'hot' iteration body concludes multiple procedure calls, higher speculative procedure level speedup can be achieved than that in loop level speculation.