Mixing static and dynamic strategies for high performance and low area reconfigurable systems. (1st January 2012)

• Record Type: Journal Article
• Authors: Rutzig, Mateus Beck; Beck, Antonio Carlos Schneider
• Is Part Of: International journal of high performance systems architecture. Volume 4:Number 1(2012)
• Page Start: 13
• Page End: 24
• Publication Date: 2012-01-01
• Subjects: reconfigurable hardware -- reconfigurable computing -- high performance architecture -- reconfigurable processors -- ALU array architecture -- data flow graphs -- power consumption -- energy consumption; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

Reconfigurable architectures can be seen as a possible solution to increase performance of current embedded systems. While dynamic reconfigurable systems present different degrees of adaptability at the price of huge area overhead, static exploitation tools can be used at design time to generate a tailored reconfigurable unit with small area requirements. However, the speedup using static tools will be limited only to the specific application set previously analysed. Therefore, we propose a technique that presents the best compromise between both approaches. After a high performance and low-power reconfigurable unit, optimised in area, is produced by a static exploitation tool, it is coupled to a dynamic hardware mechanism responsible for accelerating applications not foreseen at design time. Hence, both the capability of adaptation and the binary compatibility are maintained. We are able to save up to 40% in area and 77% in power, without significant losses in performance or adaptability.