A minimalist cache coherent MPSoC designed for FPGAs. (31st May 2011)

• Record Type: Journal Article
• Authors: Tortato Junior, Jorge; Hexsel, Roberto A.
• Is Part Of: International journal of high performance systems architecture. Volume 3:Number 2/3(2011)
• Page Start: 67
• Page End: 76
• Publication Date: 2011-05-31
• Subjects: multicore -- shared memory multiprocessors -- cache coherence -- FPGA -- MPSoC -- VHDL implementation -- field programmable gate arrays; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

We describe the design and VHDL implementation of a cache coherent MPSoC named minimalist cache coherent MPSoC (MCCM). The system comprises one to eight MIPS-I processors, coherent primary data caches, memory management units, memory controller and the interconnection. We present a detailed account of the implementation, focusing on the shared memory subsystem. A simple benchmark is used to assess the overall system functionality. We compared the size of our design to that of a LEON3-based multiprocessor and found that a four-core LEON3 system needs roughly the same amount of logic/state as a six to eight cores MCCM.