High speed, low power 100 MS/s front end track-and-hold amplifier for ten-bit pipelined ADC. (11th December 2009)

• Record Type: Journal Article
• Authors: Meganathan, D.; Perinbam, Raja Paul; Deepalakshmi, R.
• Is Part Of: International journal of high performance systems architecture. Volume 2:Number 1(2009)
• Page Start: 1
• Page End: 15
• Publication Date: 2009-12-11
• Subjects: multiplying DAC -- digital to analogue converters -- MDAC -- common-mode feedback -- CMFB -- switched capacitors -- peak-to-peak -- nanometres -- nm -- mega samples per second -- MS&amp -- #47 -- s -- megahertz -- MHz -- high-performance systems architecture -- HPSA -- amplifier design -- track-and-hold amplifiers -- operational transconductance amplifiers; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

The work focuses on the design of a high speed, low power track-and-hold amplifier (THA) for ten-bit 100 MS/s pipelined analogue-to-digital converter (ADC). A wide bandwidth and high gain two-stage operational transconductance amplifier (OTA) is selected as OTA of THA. This OTA consumes less amount of power and produce less thermal noise. The bootstrap technique is employed to reduce the non-linearity error associated with the input signal. The signal swing of the circuit is allowed to exceed the supply voltage (1.8 V), which further reduces the thermal noise contributed by the circuit and increases the dynamic range (DR) of the circuit. The circuit is implemented in UMC 180 nm digital CMOS technology. The THA circuit along with the biasing circuit consumes 5.706 mW power and it achieves 81.23 dB as the spurious free dynamic range (SFDR) for 2 V output at 100 MHz sampling rate. The dynamic range of the THA is 85.94 dB. The proposed THA is simulated using SPECTRE simulator under a variety of process and temperature conditions.