Dual channel addition based FFT processor architecture for signal and image processing. (11th December 2009)

• Record Type: Journal Article
• Authors: Sahoo, Subhendu Kumar; Shekhar, Chandra; Kodali, Sudeepti; Asati, Abhijit R.; , Anu Gupta
• Is Part Of: International journal of high performance systems architecture. Volume 2:Number 1(2009)
• Page Start: 35
• Page End: 45
• Publication Date: 2009-12-11
• Subjects: discrete Fourier transform -- DFT -- FFT processors -- IFFT processors -- multipliers -- architecture -- signal processing -- image processing; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

This paper presents a novel fixed-point 16-bit word-width 16-point FFT/IFFT processor architecture designed primarily for the signal and image processing application. The 16-point FFT is realised by using Cooley-Tukey decimation in time algorithm. This approach reduces the number of required complex multiplications compared to a normal discrete Fourier transform. Since multipliers are very power hungry elements in VLSI designs, they result in significant power consumption. So, the complex multiplication operations are realised using shift-and-add operations. The proposed algorithm performs all intermediate addition operation using a novel dual channel addition technique, which avoids carry propagation delay. Only in the last stage, carry look ahead adders are used to give final result. This dual channel addition algorithm reduces the critical delay path by 42% and 38.29% as compared to traditional and Maharatna approach respectively.