An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip. (15th October 2007)
- Record Type:
- Journal Article
- Title:
- An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip. (15th October 2007)
- Main Title:
- An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip
- Authors:
- Ali, Muhammad
Welzl, Michael
Hessler, Sven
Hellebrand, Sybille - Abstract:
- Recent advances in the silicon technology is enabling the VLSI chips to accommodate billions of transistors; leading toward incorporating hundreds of heterogeneous components on a single chip. However, it has been observed that the scalability of chips is posing grave problems for the current interconnect architecture which is unable to cope with the growing number of components on a chip. To remedy the inefficiency of buses, researchers have explored the area of computer networks besides exploring parallel computing to come up with viable solutions for billion transistor chips. The outcome is a novel and scalable communication paradigm for future System on Chips (SoCs) called as Network on Chips (NoC). However, as the chip scales, the probability of both permanent and temporary faults is also increasing, making Fault Tolerance (FT) a key concern in scaling chips. Alpha particle emissions, Gaussian noise on channels are some of the reasons which introduce transient faults in the data. Besides that, due to electromigration of conductors, corrosion or aging factors, on-chip modules or links may suffer permanent damage. This paper proposes a comprehensive solution to deal with both permanent and transient errors affecting the VLSI chips. On the one hand we present an efficient packet retransmission mechanism to deal with packet corruption or loss due to transient faults. On the other hand, we propose a deterministic routing mechanism which routes packets on alternate paths whenRecent advances in the silicon technology is enabling the VLSI chips to accommodate billions of transistors; leading toward incorporating hundreds of heterogeneous components on a single chip. However, it has been observed that the scalability of chips is posing grave problems for the current interconnect architecture which is unable to cope with the growing number of components on a chip. To remedy the inefficiency of buses, researchers have explored the area of computer networks besides exploring parallel computing to come up with viable solutions for billion transistor chips. The outcome is a novel and scalable communication paradigm for future System on Chips (SoCs) called as Network on Chips (NoC). However, as the chip scales, the probability of both permanent and temporary faults is also increasing, making Fault Tolerance (FT) a key concern in scaling chips. Alpha particle emissions, Gaussian noise on channels are some of the reasons which introduce transient faults in the data. Besides that, due to electromigration of conductors, corrosion or aging factors, on-chip modules or links may suffer permanent damage. This paper proposes a comprehensive solution to deal with both permanent and transient errors affecting the VLSI chips. On the one hand we present an efficient packet retransmission mechanism to deal with packet corruption or loss due to transient faults. On the other hand, we propose a deterministic routing mechanism which routes packets on alternate paths when a communication link or a router suffers permanent failure. … (more)
- Is Part Of:
- International journal of high performance systems architecture. Volume 1:Number 2(2007)
- Journal:
- International journal of high performance systems architecture
- Issue:
- Volume 1:Number 2(2007)
- Issue Display:
- Volume 1, Issue 2 (2007)
- Year:
- 2007
- Volume:
- 1
- Issue:
- 2
- Issue Sort Value:
- 2007-0001-0002-0000
- Page Start:
- 113
- Page End:
- 123
- Publication Date:
- 2007-10-15
- Subjects:
- network-on-chip -- NoC -- fault tolerance -- self-healing -- dynamic routing -- reliable packet delivery -- VLSI -- packet retransmission
Computer architecture -- Periodicals
Computer systems -- Periodicals
High performance computing -- Periodicals
004.205 - Journal URLs:
- http://www.inderscience.com/jhome.php?jcode=ijhpsa ↗
http://www.inderscience.com/ ↗ - Languages:
- English
- ISSNs:
- 1751-6528
- Deposit Type:
- Legaldeposit
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- Available online (eLD content is only available in our Reading Rooms) ↗
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British Library STI - ELD Digital store - Ingest File:
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