Chip multiprocessor based on data-driven multithreading model. (20th April 2007)

• Record Type: Journal Article
• Authors: Stavrou, Kyriakos; Kyriacou, Costas; Evripidou, Paraskevas; Trancoso, Pedro
• Is Part Of: International journal of high performance systems architecture. Volume 1:Number 1(2007)
• Page Start: 34
• Page End: 43
• Publication Date: 2007-04-20
• Subjects: parallelism -- dataflow -- chip multiprocessors -- CMP -- data-driven multithreading -- DDM -- speedup -- power consumption -- communication delay -- synchronisation overheads -- performance evaluation -- memory wall limitation -- high performance -- systems architecture; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

Although the dataflow model of execution, with its obvious benefits, has been proposed for a long time, it has not yet been successfully exploited. Nevertheless, as traditional systems have recently started to reach their limits in delivering higher performance, new models of execution that use dataflow-like concepts are being studied. Among these, Data-Driven Multithreading (DDM) is a multithreading model that effectively hides the communication delay and synchronisation overheads. In DDM threads are scheduled as soon as their input data has been produced, that is, in a dataflow-like way. In addition to presenting a motivation to the dataflow model of execution, this paper also presents an overview of the DDM project. In particular, it focuses on the Chip Multiprocessor (CMP) implementation using the DDM model, its hardware, run-time system and performance evaluation. The DDM-CMP inherits the benefits of both the DDM model which allows to overcome the memory wall limitation and the CMP which offers a simpler design, higher degree of parallelism and larger power-performance efficiency, therefore overcoming the power wall. Preliminary experimental results show a significant benefit in terms of both speedup and power consumption, making the DDM-CMP architecture an attractive architecture for future processors.