Hardware support for early register release. (11th November 2005)

• Record Type: Journal Article
• Authors: Monreal, Teresa; Vinals, Víctor; Gonzalez, Antonio; Valero, Mateo
• Is Part Of: International journal of high performance computing and networking. Volume 3:Number 2/3(2005)
• Page Start: 83
• Page End: 94
• Publication Date: 2005-11-11
• Subjects: register renaming -- out-of-order processors -- register files -- optimisation -- register releasing -- precise exceptions; High performance computing -- Periodicals; Computer networks -- Periodicals; High performance computing; Periodicals; 004.05
• Languages: English
• ISSNs: 1740-0562

Abstract

Register files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is closely related to the size and number of ports of the register file. In conventional register-renaming schemes, register releasing is conservatively done only after the instruction that redefines the same register is committed. Instead, we propose a scheme that releases registers as soon as the processor knows that there will be no further use of them. We present two early releasing hardware implementations with different performance/complexity trade-offs. Detailed cycle-level simulations show either a significant speedup for a given register file size, or a reduction in register file size for a given performance level.