Control-theoretic adaptive cache-fair scheduling of chip multiprocessor systems. (June 2018)

• Record Type: Journal Article
• Authors: Arslan, Huseyin G; Tian, Yu-Chu; Li, Fenglian; Peng, Chen; Fei, Min-Rui
• Is Part Of: Transactions of the Institute of Measurement and Control. Volume 40:Number 10(2018)
• Page Start: 3095
• Page End: 3104
• Publication Date: 2018-06
• Subjects: Scheduling -- feedback scheduling -- chip multiprocessor -- modelling -- adaptive control; Automatic control -- Periodicals; Measuring instruments -- Periodicals; Commande automatique -- Périodiques; Mesure -- Instruments -- Périodiques; 681.2
• DOI: 10.1177/0142331217715064
• Languages: English
• ISSNs: 0142-3312

Abstract

In chip multiprocessor scheduling, cache memory awareness is critical. However, most existing cache-aware multiprocessor scheduling methods are static and open-loop and thus do not work well in dynamic environments. To address this challenging problem, a control-theoretic approach is presented in this paper for adaptive cache-fair multiprocessor scheduling. The adaptive cache-fair multiprocessor scheduling uses process models to estimate the shared cache size requirements and the instruction count variations of the threads running on multiprocessor cores. Then, it feeds the estimated information back to an adaptive controller. Designed from the process models, the controller decides processor cycle re-allocation through model computation to maintain the instruction counts of the multiple threads at their desired values. The effectiveness of the adaptive cache-fair multiprocessor scheduling is demonstrated through examples.