Code compression in DSP processor systems. (6th January 2009) - Saastamoinen, Piia; Saastamoinen, Ilkka; Nurmi, Jari
In order to meet the demands set for time-to-market, chip size, system speed, and power, the designers are forced to continuously seek for new methods to make the optimisation and detailed refining of their designs automatically. Code compression is one possibility to go around some or even all of these design problems. With our compression methods, the memory footprint can be reduced by up to 45%, already including the area penalty created by an on-chip decompression engine. The decompression block is located between processor core and program memory. Thus the core does not need to be modified and also the performance is preserved. In addition to memory savings, memory related dynamic power consumption is reduced by 33%.