A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. (6th January 2009)

• Record Type: Journal Article
• Authors: Ayala, Jose L.; Lopez-Vallejo, Marisa; Lopez-Barrio, Carlos A.; Veidenbaum, Alexander
• Is Part Of: International journal of embedded systems. Volume 3:Number 4(2008)
• Page Start: 285
• Page End: 293
• Publication Date: 2009-01-06
• Subjects: register file -- in-order architectures -- power reduction -- instruction predecode -- hardware approach -- energy consumption -- unused registers -- control logic; Embedded computer systems -- Periodicals; 004.16
• Languages: English
• ISSNs: 1741-1068

Abstract

This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into the low-power state after the instruction use. This technique achieves an 85% energy reduction with no performance penalty.