Integrated modelling and generation of a reconfigurable network-on-chip. (6th June 2006)

• Record Type: Journal Article
• Authors: Ching, Doris; Schaumont, Patrick; Verbauwhede, Ingrid
• Is Part Of: International journal of embedded systems. Volume 1:Number 3/4(2005)
• Page Start: 218
• Page End: 227
• Publication Date: 2006-06-06
• Subjects: design methodology -- integrated modelling -- system analysis -- system design -- multiprocessor interconnection -- reconfigurable network-on-chip -- reconfigurable architectures -- NOC -- simulation -- embedded systems -- flexible reconfiguration; Embedded computer systems -- Periodicals; 004.16
• Languages: English
• ISSNs: 1741-1068

Abstract

While a communication network is a critical component for an efficient system-on-chip multiprocessor, there are few approaches available to help with system-level architectural exploration of such a specialised interconnection network. This paper presents an integrated modelling, simulation and implementation tool. The network architecture can be co-simulated with embedded-software to obtain cycle-accurate performance metrics. This allows an energy and performance tuning of the NOC. Next it can be converted into VHDL for implementation. We discuss our approach by designing a flexible network-on-chip and present implementation results. The performance of our automatically generated network is comparable with a reference design directly developed in HDL.