An ADC BIST using on-chip ramp generation and digital ORA. (November 2018) - M, Senthil Sivakumar; S P, Joy Vasantha Rani
Abstract: This paper presents an on-chip built-in self-test technique for testing an ADC. The conventional test of a mixed signal element has performed through DSP based tester with the help of an arbitrary waveform and a signal digitizer but it is consuming more time and cost. Hence, the testing strategy has started an on-chip BIST based testing scheme to control the testing issues. An on-chip ramp generator based BIST technique has proposed for testing static characteristics of ADC. The evaluation procedure of this BIST consists of test pattern generation and output response analysis. A novel cascode current mirror based analog linear ramp generator has used to generate the test pattern through fast switching TIQ comparator based ADC. Output response analyzer evaluates switching positions of binary code for computing the static parameters. The proposed ADC BIST has implemented in 0.18 μm technology with the supply voltage of 1.8 V.