All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator. (November 2018)

• Record Type: Journal Article
• Authors: Park, Young Jun; Parekh, Parth; Yuan, Fei
• Is Part Of: Microelectronics journal. Volume 81(2018)
• Page Start: 179
• Page End: 191
• Publication Date: 2018-11
• Subjects: Time-mode circuits -- ΔΣ time-to-digital converter (TDC) -- Bi-directional gated delay line (BDGDL) -- Time integrators; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.05.010
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents bi-directional gated delay line (BDGDL) time integrators featuring full compatibility with technology scaling, rapid integration, low power consumption, and built-in digitization, and their applications in all-digital first-order ΔΣ time-to-digital converters (TDCs). The architecture of the BDGDL time integrators, both single-ended and differential, is presented. The imperfections of the BDGDL time integrators are investigated. Two first-order ΔΣ TDCs, one with the single-ended BDGDL time integrator and the other with the differential BDGDL time integrator, are designed in an IBM 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM4 device models. The SNDR of the TDC with the differential BDGDL time integrator and a sinusoidal time input of amplitude 430 ps and frequency 231 kHz is 38 dB. The time resolution of the TDC is 6.7 ps and its power consumption is 243 μW.