SLIM-ADC: Spin-based Logic-In-Memory Analog to Digital Converter leveraging SHE-enabled Domain Wall Motion devices. (November 2018)

• Record Type: Journal Article
• Authors: Salehi, Soheil; DeMara, Ronald F.
• Is Part Of: Microelectronics journal. Volume 81(2018)
• Page Start: 137
• Page End: 143
• Publication Date: 2018-11
• Subjects: Signal conversion -- Boolean logic -- In-memory computation -- Beyond-CMOS devices -- Spin-Hall Effect Domain Wall Motion; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.09.012
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper devises a novel Analog to Digital Converter (ADC) framework for energy-aware acquisition of analog signals with Logic-in-Memory capabilities. The beyond-CMOS hardware architecture has been designed to minimize the overall cost of signal acquisition. Spin-Hall Effect driven Domain Wall Motion (SHE-DWM) devices are utilized to realize the proposed framework called Spin-based Logic-In-Memory ADC (SLIM-ADC) . Our simulation results indicate that the proposed SLIM-ADC offers ∼200 fJ energy consumption on average for each analog conversion or logic operation with up to 1 GHz speed. Furthermore, our results indicate that the proposed SLIM-ADC outperforms other state of the art spin-based ADC designs by offering ∼5.45 mW improved power dissipation on average. Additionally, a Majority Gate (MG)-based Full-Adder (MG-FA) is implemented using the proposed SLIM-ADC. Our results show that the proposed MG-FA offers ∼2.9-fold reduced power dissipation on average and ∼1.7-fold reduced delay on average compared to the state of the art Full-Adder designs reported herein.